1. Field of the Invention
The present invention relates to a signal generating apparatus, and more particularly, to a signal generating apparatus for generating a power-on-reset signal.
2. Description of the Prior Art
When typical electronic systems are being booted or reset, the supply voltages thereof require some time to climb to their normal levels. This means that, before the supply voltages reach their normal voltage levels, all signal processing related circuitry should be shut down in case of malfunction. Once the normal voltages are attained, a power-on-reset signal is required to notify the electronic systems to begin normal signal processing.
Please refer to FIG. 1, which is a diagram of a conventional power-on-reset signal generating apparatus 100. The power-on-reset signal generating apparatus 100 includes a bandgap circuit 110, a comparator 120 and a voltage dividing circuit 130. A reference voltage VREF, which is generated by the bandgap circuit 110, is very insensitive to process, voltage and temperature (PVT) variations due to the circuit characteristics thereof. The reference voltage VREF is therefore very stable and suitable to be utilized as a comparison reference. The comparator 120 will receive the reference voltage VREF generated by the bandgap circuit 110 and a comparison voltage VCOMP which is generated by the voltage dividing circuit 130 according to a supply voltage VSUP, and compare the reference voltage VREF with the comparison voltage VCOMP to generate a power-on-reset signal PORSB1. Please refer to FIG. 2, which is an ideal diagram of partial signals of the power-on-reset signal generating apparatus 100 shown in FIG. 1. When the supply voltage VSUP climbs to a certain voltage level, the comparison voltage VCOMP also increases to a level higher than the reference voltage VREF. At this moment, the comparator 120 will output the power-on-reset signal PORSB1 as “1”, i.e. a high voltage level. However, since the supply voltage VSUP is also utilized to bias the bandgap circuit 110, when the supply voltage VSUP climbs up rapidly and the reference voltage VREF generated by the bandgap circuit 110 remains unstable, an erroneous comparison result may occur, which leads the power-on-reset signal PORSB1 to be changed to “1” prematurely. Please refer to FIG. 3, which is a diagram of partial erroneous signals that result from erroneous comparison by the power-on-reset signal generating apparatus 100 shown in FIG. 1. As shown in FIG. 3, during the interval when the supply voltage VSUP climbs rapidly, the comparator 120 may encounter misjudgment, leading to an erroneous power-on-reset signal PORSB1.
Please refer to FIG. 4, which is a diagram of another conventional power-on-reset signal generating apparatus 400. The power-on-reset signal generating apparatus 400 includes three diode-connected transistors M1. M2 and M3 coupled in series, a hysteresis circuit 410 (for example, a Schmitt trigger) and a buffer or invertor circuit 420. As the supply voltage VSUP increases, the transistors M1, M2 and M3 will also be switched to conduct currents, and a voltage VM is outputted simultaneously. As shown in FIG. 4, the voltage VM is a gate-source voltage of the transistor M1 plus a gate-source voltage of the transistor M2. When the voltage VM is larger than a threshold voltage of the hysteresis circuit 410, the power-on-reset signal PORSB2 outputted by the power-on-reset signal generating apparatus 400 will be changed to “1”. Therefore, when the supply voltage VSUP climbs to an amount sufficient to switch on the transistors M1, M2 and M3, the power-on-reset signal PORSB2 will be changed to “1”. The operations of the transistors M1, M2 and M3 are very susceptible to process or temperature variations, however, and the conventional power-on-reset signal generating apparatus 400 is not able to provide a stable power-on-reset signal as a result.